JPS64859B2 - - Google Patents

Info

Publication number
JPS64859B2
JPS64859B2 JP57199235A JP19923582A JPS64859B2 JP S64859 B2 JPS64859 B2 JP S64859B2 JP 57199235 A JP57199235 A JP 57199235A JP 19923582 A JP19923582 A JP 19923582A JP S64859 B2 JPS64859 B2 JP S64859B2
Authority
JP
Japan
Prior art keywords
circuit
output
digital signal
amplitude
bit synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57199235A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5989052A (ja
Inventor
Gozo Kage
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57199235A priority Critical patent/JPS5989052A/ja
Publication of JPS5989052A publication Critical patent/JPS5989052A/ja
Publication of JPS64859B2 publication Critical patent/JPS64859B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP57199235A 1982-11-12 1982-11-12 ビツト同期回路 Granted JPS5989052A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57199235A JPS5989052A (ja) 1982-11-12 1982-11-12 ビツト同期回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57199235A JPS5989052A (ja) 1982-11-12 1982-11-12 ビツト同期回路

Publications (2)

Publication Number Publication Date
JPS5989052A JPS5989052A (ja) 1984-05-23
JPS64859B2 true JPS64859B2 (en]) 1989-01-09

Family

ID=16404401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57199235A Granted JPS5989052A (ja) 1982-11-12 1982-11-12 ビツト同期回路

Country Status (1)

Country Link
JP (1) JPS5989052A (en])

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH063904B2 (ja) * 1986-05-28 1994-01-12 シャープ株式会社 クロック信号再生回路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923496B2 (ja) * 1977-08-25 1984-06-02 富士通株式会社 タイミング抽出方式

Also Published As

Publication number Publication date
JPS5989052A (ja) 1984-05-23

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